Publications

Books:

  1. Y. S. Chauhan, G. Pahwa, A. Dasgupta, D. Lu, S. Venugopalan, S. Khandelwal, J. Duarte, N. Paydavosi, A. Niknejad, C. Hu, “FinFET/GAA Modeling for IC Simulation and Design: Using the BSIM-CMG Standard 2nd Edition”, Academic Press – Elsevier, 2024.

Publications:
Google Scholar Profile: Google Scholar   Research Gate Profile:  ResearchGate

2025

Journal articles:

  1. S. S. Parihar, S. Kumar, S. Chatterjee, G. Pahwa, Y. S. Chauhan and H. Amrouch, “Cryogenic Hyper-Dimensional In-Memory Computing using Ferroelectric TCAM”, in IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2025.
  2. Y. H. Zarkob, A. Sharma, G. Pahwa, D. Nandi, C. K. Dabhi, V. Kubrak, B. Peddenpohl, M. Tang, C. Hu and Y. S. Chauhan, “Impact Ionization in LDMOS Transistors: Improved Compact Model and Asymmetry under Forward and
    Reverse Modes of Operation”, in IEEE Journal of the Electron Devices Society, 2025.

Conference articles

  1. D. Raja, Y. Machhiwar, K. Tripathi, G. Pahwa, Harshit Agarwal, “Performance Analysis of Advanced Ferroelectric HfO2 − ZrO2 Superlattice Gate Stack Transistor with Multi-Phase Ferroelectric Order,” accepted in IEEE Electron Devices Technology and Manufacturing (EDTM), 2025.

2024
Journal articles:

  1. S. S. Parihar, G. Pahwa, B. Mohammad, Y. S. Chauhan and H. Amrouch, “Novel Trade-offs in 5nm FinFET SRAM Arrays at Extreme Low Temperatures,” in IEEE Transactions on Quantum Engineering, 2025.
  2. C. K. Dabhi, G. Pahwa, S. Salahuddin, and C. Hu, “Boltzmann-Statistics Aware Non-Quasi-Static-Charge Model for IC Simulations“, in IEEE Transactions on Electron Devices, 2024.
  3. G. Gill, A. Singhal, G. Pahwa, A. Lahgere, H. Agarwal, “A Comprehensive Analysis of Safe Operating Area Limits in Ferroelectric-Based DEMOS“, in IEEE Transactions on Electron Devices, 2024.
  4. A. Singhal, Y. Machhiwar, S. Kumar, G. Pahwa, and H. Agarwal, “ANN-based framework for modeling process induced variation using BSIM-CMG unified model“, in Solid State Electronics, 2024, p. 108988.
  5. G. Pahwa, S. Salahuddin, and C. Hu, “An All-Region BSIM Thin Film Transistor Model for Display and BEOL 3D Integration Applications”, in IEEE Transactions on Electron Devices, 2024.
  6. A. Sharma, Y. H. Zarkob, G. Pahwa, C. K. Dabhi, R. Goel, H. Agarwal, V. Kubrak, M. Tang, M. Treiber, C. Hu, and Y. S. Chauhan, “Compact Modeling of Impact Ionization and Conductivity Modulation in LDMOS Transistors,” in IEEE Transactions on Electron Devices, 2024.
  7. W. Manzoor, A. K . Dutta, G. Pahwa, N. Manzoor, C. Hu, and Y. S. Chauhan, Extending Standard BSIM-BULK Model to Cryogenic Temperatures, in IEEE Transactions on Electron Devices, 2024.
  8. A. Singhal, G. Pahwa, and H. Agarwal, “A Novel Physics Aware ANN Based Framework for BSIM-CMG Model Parameter Extraction,” in IEEE Transactions on Electron Devices, vol. 71, no. 5, pp. 3307-3314, May 2024.
  9. C. K. Dabhi, D. Rajasekharan, G. Pahwa, D. Nandi, N. Karumuri, S. Turuvekere, A. Dutta, B. Swaminathan, S. Srihari, Y. S. Chauhan, S. Salahuddin, and C. Hu, “Symmetric BSIM-SOI: A Compact Model for Dynamically Depleted SOI MOSFETs – Part I”, in IEEE Transactions on Electron Devices, 2024.
  10. C. K. Dabhi, D. Nandi, D. Rajasekharan, G. Pahwa, N. Karumuri, S. Turuvekere, A. Dutta, B. Swaminathan, S. Srihari, Y. S. Chauhan, S. Salahuddin, and C. Hu, “Symmetric BSIM-SOI: A Compact Model for Partially Depleted SOI MOSFETs – Part II”, in IEEE Transactions on Electron Devices, 2024.

Conference articles

  1. H. Agarwal and G. Pahwa, “A Wrapper Model for ESD-FET Simulation and Analysis“, in MOS-AK Workshop, Silicon Valley, Dec. 2024.
  2. A. Singhal, G. Gill, A. Lahgere, G. Pahwa, and Harshit Agarwal, “Improved Compact Modeling of Snapback Behaviour in ESD MOSFETs”, in International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2024.
  3. S. S. Parihar, G. Pahwa, Y. S. Chauhan, and H. Amrouch, “Impact of Self-Heating in 5nm FinFETs at Cryogenic Temperatures for Reliable Quantum Computing: Device-Circuit Interaction”, accepted in IEEE International Reliability Physics Symposium (IRPS), 2024.
  4. B. Hien, M. Walter, V. M. van Santen, F. Klemme, S. S. Parihar, G. Pahwa, Y. S. Chauhan, H. Amrouch, and Robert Will, “Technology Mapping for Cryogenic CMOS Circuits”, accepted in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2024.
  5. Aayush, G. Pahwa, Y. S. Chauhan, “Design Space Exploration of Negative Capacitance Effect in MFIM Structure: A 3D Phase Field Approach”, in IEEE Electron Devices Technology and Manufacturing (EDTM), 2024.
  6. Y. H. Zarkob, A. Sharma, G. Pahwa, D. Nandi, C. K. Dabhi, V. Kubrak, B. Peddenpohl, M. Tang, C. Hu and Y. S. Chauhan, “Compact Modeling and Experimental Validation of Reverse Mode Impact Ionization in LDMOS Transistors within the BSIM-BULK Framework”, in IEEE Electron Devices Technology and Manufacturing (EDTM), 2024.

2023
Journal articles:

  1. P. Kumar, A. Nonaka, R. Jambunathan, G. Pahwa, and S. Salahuddin, Z. Yao. “FerroX: A GPU-accelerated, 3D Phase-Field Simulation Framework for Modeling Ferroelectric Devices”, in Computer Physics Communications, pages 108757, 2023, https://doi.org/10.1016/j.cpc.2023.108757.
  2. S. S. Parihar, V. M. van Santen, S. Thomann, G. Pahwa, Y. S. Chauhan, and H. Amrouch, “Cryogenic CMOS for Quantum Processing: 5nm FinFET based SRAM Arrays at 10K”, accepted in IEEE Transactions on Circuits and Systems I, 2023.
  3. P. R. Genssler, F. Klemme, S. S. Parihar, G. Pahwa, Y. S. Chauhan, and H. Amrouch, “On the Plausibility of Cryogenic CMOS SoC at 5nm FinFET for Quantum Measurement Classification”, in IEEE Transactions on Quantum Engineering, vol. 4, pp. 1-11, 2023, Art no. 5500611, doi: 10.1109/TQE.2023.3300833.
  4. S. S. Parihar, S. Thomann, G. Pahwa, Y. S. Chauhan and H. Amrouch, “Cryogenic In-Memory Computing for Quantum Processors Using Commercial 5-nm FinFETs,” in IEEE Open Journal of Circuits and Systems, vol. 4, pp. 258-270, 2023, doi: 10.1109/OJCAS.2023.3309478.
  5. G. Gill, Y. Machhiwar, G. Pahwa, C. Hu, and H. Agarwal, “Comprehensive High Voltage Parameter Extraction Strategy for BSIM-BULK HV Model”, in IEEE Transaction on Electron Devices, 2023, doi: 10.1109/TED.2023.3257121.
  6. G. Gill, A. Singhal, G. Pahwa, C. Hu and H. Agarwal, “Compact Modeling of Impact Ionization in High-Voltage Devices,” in IEEE Transactions on Electron Devices, 2023, doi: 10.1109/TED.2023.3253101.
  7. G. Pahwa, A. Sharma, R. Goel, G. Gill, H. Agarwal, Y. S. Chauhan, and C. Hu “Robust Compact Model of High Voltage MOSFETs’ Drift Region “, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 42, no. 1, pp. 337-340, Jan. 2023, doi: 10.1109/TCAD.2022.3172599.

Conference articles:

  1. S. S. Parihar, S. Chatterjee, G. Pahwa, Y. S. Chauhan, and H. Amrouch, “Modeling and Benchmarking 5nm Ferroelectric FinFET from Room Temperature down to Cryogenic Temperatures”, in IEEE International Conference on Nanotechnology (NANO), Jeju City, Korea, pp. 643-648, doi: 10.1109/NANO58406.2023.10231310. 2023.
  2. S. S. Parihar, S. Thomann, G. Pahwa, Y. S. Chauhan, and H. Amrouch, “5nm FinFET Cryogenic SRAM for Quantum Computing”, in Device Research Conference (DRC), San Francisco, 2023, doi: 10.1109/DRC58590.2023.10186959.
  3. V. M. van Santen, M. Walter, F. Klemme, S. S. Parihar, G. Pahwa, Y. S. Chauhan, R. Wille, and H. Amrouch, “Design Automation for Cryogenic CMOS Circuits”, accepted in Design Automation Conference (DAC), San Francisco, 2023, doi: 10.1109/DAC56929.2023.10247824.
  4. S. S. Parihar, G. Pahwa, J. Huang, W. Wang, K. Imura, C. Hu, and Y. S. Chauhan, “Cryogenic Characterization and Model Extraction of 5nm Technology Nodes FinFETs”, in IEEE Electron Devices Technology and Manufacturing (EDTM), 2023, doi: 10.1109/EDTM55494.2023.10102942.
  5. A. Singhal, G. Gill, G. Pahwa, C. Hu, and H. Agarwal, “An Improved Robust Infinitely Differentiable Drift Resistance Model for BSIM High Voltage Compact Model”, accepted in IEEE Electron Devices Technology and Manufacturing (EDTM), 2023, doi: 10.1109/EDTM55494.2023.10103122.
  6. P. Kumar, A. Nonaka, R. Jambunathan, G. Pahwa, and S. Salahuddin, Z. Yao. “FerroX: A GPU-accelerated, 3D Phase-Field Simulation Framework for Modeling Ferroelectric Devices”, APS March Meeting, Bulletin of the American Physical Society, 2023.

 2022
Journal articles:

  1. G. Pahwa, S. Salahuddin, and C. Hu, “Critical Importance of Nonuniform Polarization and Fringe Field Effects for Scaled Ferroelectric FinFET Memory,” in IEEE Transactions on Electron Devices, vol. 69, no. 9, pp. 4900-4908, Sept. 2022, doi: 10.1109/TED.2022.3190252.
  2. C. -T. Tung, G. Pahwa, S. Salahuddin, and C. Hu, “A Compact Model of Nanoscale Ferroelectric Capacitor,” in IEEE Transactions on Electron Devices, vol. 69, no. 8, pp. 4761-4764, Aug. 2022, doi: 10.1109/TED.2022.3181573.
  3. C. -T. Tung, G. Pahwa, S. Salahuddin, and C. Hu, “A Compact Model of Ferroelectric Field-Effect Transistor,” in IEEE Electron Device Letters, vol. 43, no. 8, pp. 1363-1366, Aug. 2022, doi: 10.1109/LED.2022.3182141.
  4. C. -T. Tung, G. Pahwa, S. Salahuddin, and C. Hu, ” A Compact Model of Metal-Ferroelectric-Insulator-Semiconductor Tunnel Junction,” in IEEE Transactions on Electron Devices, vol. 69, no. 1, pp. 414-418, Jan. 2022, doi: 10.1109/TED.2021.3130857.

Conference articles:

  1. G. Pahwa, A. Dasgupta, C. T. Tung, M.Y. Kao, C. K. Dabhi, S. Sarker, S. Salahuddin, C. Hu ” Compact Modeling of Emerging IC Devices for Technology-Design Co-development, IEEE International Electron Devices Meeting (IEDM), San Francisco, USA, Dec. 2022, doi: 10.1109/IEDM45625.2022.10019433.
  2. A. Sharma, Y. H. Zarkob, R. Goel, C. K. Dabhi, G. Pahwa, C. Hu and Y. S.Chauhan, “Recent Enhancements in the Standard BSIM-BULK MOSFET Model”, in International Conference on Emerging Electronics (ICEE), Bangalore, Dec. 2022, doi: 10.1109/ICEE56203.2022.10118345.
  3. A. Kumar, G. Pahwa, A. K. Behera, A. Bulusu, S. Mehrotra and A. Dasgupta, “Analysis and Modeling of Flicker Noise in Ferroelectric FinFETs”, in International Conference on Emerging Electronics (ICEE), Bangalore, Dec. 2022, doi: 10.1109/ICEE56203.2022.10118175.
  4. C. K. Dabhi, G. Pahwa, S. Salahuddin, and C. Hu, “Compact Model for Trap Assisted Tunneling based GIDL,” in Device Research Conference (DRC), Ohio, June 2022, doi: 10.1109/DRC55272.2022.9855798.

2021
Journal articles:

  1.  N. Pandey, G. Pahwa, and Y. S. Chauhan, “Addressing source to drain tunneling in extremely scaled Si-transistors using negative capacitance,” Solid-State Electronics, vol. 186, 108189, 2021, https://doi.org/10.1016/j.sse.2021.108189.
  2. C. -T. Tung, G. Pahwa, S. Salahuddin, and C. Hu, “A Compact Model of Polycrystalline Ferroelectric Capacitor,” in IEEE Transactions on Electron Devices, vol. 68, no. 10, pp. 5311-5314, Oct. 2021, doi: 10.1109/TED.2021.3100814.
  3. G. Pahwa, P. Kushwaha, A. Dasgupta, S. Salahuddin, and C. Hu, “Compact Modeling of Temperature Effects in FDSOI and FinFET Devices Down to Cryogenic Temperatures,” in IEEE Transactions on Electron Devices, vol. 68, no. 9, pp. 4223-4230, Sept. 2021, doi: 10.1109/TED.2021.3097971.
  4. O. Prakash, A. Gupta, G. Pahwa, Y. S. Chauhan, and H. Amrouch, “On the Critical Role of Ferroelectric Thickness for Negative Capacitance Device-Circuit Interaction,” in IEEE Journal of the Electron Devices Society, vol. 9, pp. 1262-1268, Sep. 2021, doi: 10.1109/JEDS.2021.3110486.
  5.  O. Prakash, G. Pahwa, C. K. Dabhi, Y. S. Chauhan, and H. Amrouch, “Impact of Self-Heating on Negative-Capacitance FinFET: Device-Circuit Interaction,” in IEEE Transactions on Electron Devices, vol. 68, no. 4, pp. 1420-1424, April 2021, doi: 10.1109/TED.2021.3059180.
  6. G. Paim, G. Zervakis, G. Pahwa, Y. S. Chauhan, E. da Costa, C. Antônio and S. Bampi, J. Henkel, and H. Amrouch, “On the Resiliency of NCFET Circuits Against Voltage Over-Scaling,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 4, pp. 1481-1492, April 2021, doi: 10.1109/TCSI.2021.3058451.
  7. M. -Y. Kao, Y. -H. Liao, G. Pahwa, A. Dasgupta, S. Salahuddin, and C. Hu, “Energy Storage and Reuse in Negative Capacitance,” in IEEE Transactions on Electron Devices, vol. 68, no. 4, pp. 1861-1865, April 2021, doi: 10.1109/TED.2021.3055177.
  8. G. Pahwa, A. D. Gaidhane, A. Agarwal and Y. S. Chauhan, “Assessing Negative-Capacitance Drain-Extended Technology for High-Voltage Switching and Analog Applications,” in IEEE Transactions on Electron Devices, vol. 68, no. 2, pp. 679-687, Feb. 2021, doi: 10.1109/TED.2020.3044554.

Conference articles:

  1. O. Prakash, A. Gupta, G. Pahwa, Y. S. Chauhan and H. Amrouch, “On the Critical Role of Ferroelectric Thickness for Negative Capacitance Transistor Optimization,” IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 2021, doi: 10.1109/EDTM50988.2021.9420894.

2020
Journal articles:

  1. O. Prakash, A. Gupta, G. Pahwa, J. Henkel, Y. S. Chauhan, and H. Amrouch, “Impact of Interface Traps on Negative Capacitance Transistor: Device and Circuit Reliability,” in IEEE Journal of the Electron Devices Society, vol. 8, pp. 1193-1201, 2020, doi: 10.1109/JEDS.2020.3022180.
  2. A. D. Gaidhane, G. Pahwa, A. Dasgupta, A. Verma, and Y. S. Chauhan, “Compact Modeling of Surface Potential, Drain Current and Terminal Charges in Negative Capacitance Nanosheet FET including Quasi-Ballistic Transport,” in IEEE Journal of the Electron Devices Society, vol. 8, pp. 1168-1176, 2020, doi: 10.1109/JEDS.2020.3019927.
  3. M. -Y. Kao, G. Pahwa, A. Dasgupta, S. Salahuddin, and C. Hu, “Analysis and Modeling of Polarization Gradient Effect on Negative Capacitance FET,” in IEEE Transactions on Electron Devices, vol. 67, no. 10, pp. 4521-4525, Oct. 2020, doi: 10.1109/TED.2020.3013569.
  4. H. Amrouch, G. Pahwa, A. D. Gaidhane, C . K. Dabhi, F. Klemme, O. Prakash, and Y. S. Chauhan, “Impact of Variability on Processor Performance in Negative Capacitance FinFET Technology,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 9, pp. 3127-3137, 2020, doi: 10.1109/TCSI.2020.2990672.
  5. A. D. Gaidhane, G. Pahwa, A. Verma, and Y. S. Chauhan, “Gate-Induced Drain Leakage in Negative Capacitance FinFETs,” in IEEE Transactions on Electron Devices, vol. 67, no. 3, pp. 802-809, March 2020, doi: 10.1109/TED.2020.2967463.

Conference articles:

  1. A.D. Gaidhane, G. Pahwa, A. Dasgupta, A. Verma, Y. S. Chauhan, “Compact Modeling of Negative Capacitance Nanosheet FET Including Quasi-Ballistic Transport,” in IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Penang, Malaysia, March, 2020, doi: 10.1109/EDTM47692.2020.911784.
  2. O. Prakash, A. Gupta, G. Pahwa, J. Henkel, Y. S. Chauhan and H. Amrouch , “Impact of Interface Traps Induced Degradation on Negative Capacitance FinFET ,” in IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Penang, Malaysia, 2020, doi: 10.1109/EDTM47692.2020.9118008.
  3. G. Bajpai, A. Gupta, O. Prakash, G. Pahwa, J. Henkel, Y. S. Chauhan, and H. Amrouch, “Impact of Radiation on Negative Capacitance FinFET,” in International Reliability Physics Symposium (IRPS), Dallas, Texas, U.S., 2020, doi: 10.1109/IRPS45951.2020.9129165.
  4. H. Amrouch, V. M. van Santen, G. Pahwa, Y. S. Chauhan and J. Henkel, “NCFET to Rescue Technology Scaling: Opportunities and Challenges (special session),” in Asia and South Pacific Design Automation Conference (ASP-DAC), Beijing, China, January, 2020, doi: 10.1109/ASP-DAC47756.2020.9045415.

2019
Journal articles:

  1. H. Amrouch, S. Salamin, G. Pahwa, A. D. Gaidhane, J. Henkel, and Y. S. Chauhan, “Unveiling the Impact of IR-drop on Performance Gain in NCFET-based Processors,” in IEEE Transactions on Electron Devices, vol. 66, no. 7, pp. 3215-3223, July 2019, doi: 10.1109/TED.2019.2916494.
  2. G. Pahwa, A. Agarwal and Y. S. Chauhan, “Numerical Investigation of Short-Channel Effects in Negative Capacitance MFIS and MFMIS Transistors: Above-Threshold Behavior,” in IEEE Transactions on Electron Devices, vol. 66, no. 3, pp. 1591-1598, March 2019, doi: 10.1109/TED.2019.2892186.

Conference articles:

  1. G. Pahwa, A. Agarwal and Y. S. Chauhan, “Evaluating Negative Capacitance Technology for RF MOS Varactors,”, in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), San Jose, USA, Oct 2019, doi: 10.1109/S3S46989.2019.9320695.
  2. S. Salamin, M. Rapp, H. Amrouch, G. Pahwa, Y. S. Chauhan, and Jörg Henkel, “NCFET-Aware Voltage Scaling,”, in IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), Lausanne, Switzerland, July 2019, doi: 10.1109/ISLPED.2019.8824802.
  3. M. Rapp, H. Amrouch, S. Salamin, G. Pahwa, Y. S. Chauhan and J. Henkel, “Performance, Power and Cooling Trade-Offs with NCFET-based Many-Cores“, in ACM/IEEE Design Automation Conference (DAC), Las Vegas, USA, June 2019, https://doi.org/10.1145/3316781.3317880.
  4. A.D. Gaidhane, G. Pahwa and Y.S. Chauhan, “Modeling of Inner Fringing Charges and Short Channel Effects in Negative Capacitance MFIS Transistor “, in Electron Devices Technology and Manufacturing (EDTM), Singapore, March 2019, doi: 10.1109/EDTM.2019.8731214.

2018
Journal articles:

  1. G. Pahwa, A. Agarwal and Y. S. Chauhan, “Numerical Investigation of Short-Channel Effects in Negative Capacitance MFIS and MFMIS Transistors: Subthreshold Behavior,” in IEEE Transactions on Electron Devices, vol. 65, no. 11, pp. 5130-5136, Nov. 2018, doi: 10.1109/TED.2018.2870519.
  2. H. Amrouch, G. Pahwa, A. D. Gaidhane, J. Henkel, and Y. S. Chauhan, “Negative Capacitance Transistor to Address the Fundamental Limitations in Technology Scaling: Processor Performance,” in IEEE Access, vol. 6, pp. 52754-52765, 2018, doi: 10.1109/ACCESS.2018.2870916.
  3. A.D. Gaidhane, G. Pahwa, A. Verma, and Y. S. Chauhan, “Compact Modeling of Drain Current, Charges, and Capacitances in Long-Channel Gate-All-Around Negative Capacitance MFIS Transistor,” in IEEE Transactions on Electron Devices, Vol. 65, Issue 5, May 2018, doi: 10.1109/TED.2018.2813059.
  4. G. Pahwa, T. Dutta, A. Agarwal, and Y. S. Chauhan, “Physical Insights on Negative Capacitance Transistors in Nonhysteresis and Hysteresis Regimes: MFMIS Versus MFIS Structures,” in IEEE Transactions on Electron Devices, Vol. 65, Issue 3, pp. 867-873, March 2018, doi: 10.1109/TED.2018.2794499.
  5. T. Dutta, G. Pahwa, A. Agarwal, and Y. S. Chauhan, “Impact of Process Variations on Negative Capacitance FinFET Devices and Circuits,” in IEEE Electron Device Letters, Vol. 39, Issue 1, Jan. 2018, doi: 10.1109/LED.2017.2770158.

Conference articles:

  1. K. Qureshi, G. Pahwa , and Y.S. Chauhan, “Impact of Linear Intergranular Variation in Remnant Polarization on Negative Capacitance Field Effect Transistor“, in International Conference on Emerging Electronics (ICEE), Bangalore, Dec. 2018, doi: 10.1109/ICEE44586.2018.8937999.
  2. A.D. Gaidhane, G. Pahwa and Y.S. Chauhan, “Compact Modeling of Drain Current in Double Gate Negative Capacitance MFIS Transistor“, in International Conference on Emerging Electronics (ICEE), Bangalore, Dec. 2018, doi: 10.1109/ICEE44586.2018.8937923.

2017
Journal articles:

  1. T. Dutta, G. Pahwa, A. Agarwal, and Y. S. Chauhan, “Performance Evaluation of 7-nm Node Negative Capacitance FinFET-Based SRAM”, in IEEE Electron Device Letters, Vol. 38, Issue 8, Aug. 2017, doi: 10.1109/LED.2017.2712365.
  2.  G. Pahwa, T. Dutta, A. Agarwal, and Y. S. Chauhan, “Compact Model for Ferroelectric Negative Capacitance Transistor with MFIS structure,” in IEEE Transactions on Electron Devices, Vol. 64, Issue 3, pp. 1366-1374, March 2017, doi: 10.1109/TED.2017.2654066.

2016
Journal articles:

  1. G. Pahwa, T. Dutta, A. Agarwal, S. Khandelwal, S. Salahuddin, C. Hu, and Y. S. Chauhan, “Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance – Part II: Model Validation,” in IEEE Transactions on Electron Devices, vol. 63, no. 12, pp. 4986-4992, Dec. 2016, doi: 10.1109/TED.2016.2614436.
  2. G. Pahwa, T. Dutta, A. Agarwal, S. Khandelwal, S. Salahuddin, C. Hu, and Y. S. Chauhan, “Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance – Part I: Model Description,” in IEEE Transactions on Electron Devices, vol. 63, no. 12, pp. 4981-4985, Dec. 2016, doi: 10.1109/TED.2016.2614432.

Conference articles:

  1. G. Pahwa, T. Dutta, A. Agarwal, and Y. S. Chauhan, “Energy-Delay Tradeoffs in Negative Capacitance FinFET based CMOS Circuits,” in International Conference on Emerging Electronics (ICEE), Mumbai, December 2016, doi: 10.1109/ICEmElec.2016.8074416.
  2. G. Pahwa, T. Dutta, A. Agarwal, and Y. S. Chauhan, “Designing Energy Efficient and Hysteresis Free Negative Capacitance FinFET with Negative DIBL and 3.5X ION using Compact Modeling Approach“, in IEEE European Solid-State Device Research Conference (ESSDERC), Lausanne, Switzerland, Sept. 2016, doi: 10.1109/ESSDERC.2016.7599584.

2015
Conference articles:

  1. G. Pahwa, A. Agarwal, and Y. S. Chauhan, “Compact Modeling of Negative Capacitance Transistor with Experimental Validation,” in International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, Dec. 2015.
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